A conventional IC includes a PLL circuit, an external clock terminal, buffer circuits, a test terminal and a logic circuit. The logic circuit is provided with input terminals and output terminals. The PLL circuit generates master clocks based on the external clocks. The logic circuit performs a predetermined logical operation to an input signal, supplied to the input terminals, in synchronization with the master clock signals. Results of the logical operation by the logic circuit are outputted from the output terminals.
When a test is performed on the PLL circuit, an external logic analyzer is connected to the clock terminal and the test output terminal. In the test, external clocks are supplied to the clock terminal, and output clocks supplied from the test terminal are used to detect or measure the frequency and jitter of the master clock signal. In accordance with such detection results, a determination is made as to whether the PLL circuit has required characteristics.
“Jitter” is abrupt or spurious variations in the phase of the frequency modulation of a successive pulse reference to the phase of a continuous oscillator.
According to the above-described semiconductor IC, however, detected waveforms may become dull due to an impedance of a cable connected to the terminals and to the external analyzer. As a result, it is difficult to detect or measure the frequency and jitter of the PLL circuit reliably.